Single Flux Quantum One-Decimal-Digit RNS Adder

نویسندگان

  • Nada Vukovic
  • Marc J. Feldman
چکیده

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm. Chips were fabricated at HYPRES, Inc. using 1 kA/cm low-Tc Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Novel Design and Simulation of 2 Digit BCD Adders Using Reversible Gates

Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the ...

متن کامل

Pii: S0964-1807(99)00018-6

ÐResidue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single ̄ux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimaldigit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines s...

متن کامل

A fully redundant decimal adder and its application in parallel decimal multipliers

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast ...

متن کامل

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 7542008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are adva...

متن کامل

A Fast Combined Decimal Adder/Subtractor

An algorithm for a fast decimal addition is proposed. The addition is performed in two steps. First, the result of addition is produced in a decimal signed-digit format. Second, the decimal signed-digit result is converted into the non-redundant form BCD. The conversion uses a borrow generating scheme based on a parallel-prefix network. Using the flexible features of the decimal signed-digit re...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2007